Turbo Decoder Architecture for Beyond-4G Applications by Cheng-Chi Wong & Hsie-Chia Chang

Author:Cheng-Chi Wong & Hsie-Chia Chang
Language: eng
Format: epub
Publisher: Springer New York, New York, NY

The operating frequency is the decisive factor in throughput calculation of conventional turbo decoders. Although the modification to circuits can improve this factor, there is a limit to the critical path delay, and it is difficult to supply a stable clock signal with high frequency. We need other methods to further raise the decoding speed. The general idea is exploiting parallel architecture, which includes the turbo decoder level, the SISO decoder level, and the trellis stage level [45, 46]. In the turbo decoder level, multiple dedicated turbo decoders are used to decode multiple codeword blocks independently. In the SISO decoder level, every codeword block is split into several sub-blocks first, and then these sub-blocks are processed by multiple SISO decoders simultaneously. In the trellis stage level, the functional units inside the SISO decoder are duplicated to complete the computations related to two or more trellis stages within one clock cycle. This chapter will describe the features of each level. The parallel turbo decoder level is an intuitive method, so we only give a brief introduction. Our discussions center on the parallel SISO decoder level in particular because the turbo codes of 3GPP LTE-Advanced standard and IEEE 802.16m standard, or more precisely, the QPP interleaver in (1.​1) and the ARP interleaver in (1.​3) are designed to support this type of architecture. The available divisions of one codeword block and the largest parallelism in each application are stated first, then the variations of decoding speed and performance are presented. The parallel trellis stage level needs a minor modification to the decoding algorithm, and it also can be employed by the turbo decoders for above-mentioned standards. Even with the same parallelism, the gains of these levels are dissimilar, and so are their respective costs. Thus, the selection of the best parallel architecture will depend on the required throughput and hardware resource.

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